1. Field of the Invention
The present invention relates to differential comparators for producing digital outputs, and, specifically, to the implementation of process and temperature invariant hysteresis.
2. Discussion of the Related Art
In an automotive setting, to reduce the amount of wiring in the wiring harnesses, a differential bus arrangement similar to an ethernet is constructed to which several devices are connected. Since the devices share bandwidth on the bus, the differential bus must handle a high data rate. For a lengthy bus, the differential signal may be attenuated greatly in certain areas physically remote from the presently driving device. In order to receive digital information transmitted on the bus, a comparator is desired which can detect 50 mV.sub.p-p input levels with a controlled level of hysteresis that is more than 8 mV but less than 15 mV.
As illustrated in FIG. 1, the common mode input voltage to the comparator is anywhere between the supply voltages, typically +5 V and ground. Valid output data must be available in 100 ns to meet the bandwidth requirement of the differential bus configuration. To accommodate the temperature range for an automotive application, the temperature range for this application is -40 to +155 degrees Celsius. Furthermore, the design must be robust over varying process comers produced during fabrication of the integrated circuit.
Several different design approaches were considered and found not adequate for all process corners or over the extremely wide temperature range of this application.
One approach is to use a comparator constructed with a standard differential pair and loaded by cross-coupled current mirrors with greater than unity gain and connected in such a way as to exhibit regenerative positive feedback, thus creating hysteresis. See, P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, New York: Holt Rinehart and Wilson, pp. 349-356, 1987. The level of hysteresis exhibited by this design is a function of the ratio of the positive feedback, the input stage transconductance, and the speed of the comparator coming out of saturation to change state with respect to changes in the input signal. The last two effects are strong functions of temperature and process variations. Due to the fact that the internal nodes saturate during operation, this comparator changes state too slowly for the present high speed application. Furthermore, the level of hysteresis is not adjustable, but rather is fixed by the circuit design and implementation.
The speed problem exhibited by the above-described design is somewhat improved by the design of Lionel M. De Weck, High Speed Comparator Having Controlled Hysteresis, U.S. Pat. No. 4,607,671, Jun. 2, 1987. But the hysteresis in this design is still set by the transconductance of the comparator input stage and, therefore, is still heavily dependent on process comers and temperature.
The comparator disclosed by David P. Laude, Precision CMOS Comparator With Hysteresis, U.S. Pat. No. 4,940,907, Jul. 10, 1990, attempts to fix the hysteresis problem by a replica bias method. However, the gain of the amplifier is relatively low because there is essentially only one gain stage. In order to acquire signals in 100 nanoseconds, this type of comparator requires a very high supply current.
Prior art comparators suffer either from process dependence or temperature dependence on the hysteresis level, or speed and power inadequacies.